The invention relates to transistor construction and uses and, in particular, to a transistor employing nanocrystals which may be used as a memory cell or amplifier.
In recent years, it has been discovered that nanocrystals are effective in storing small amounts of electric charge in microscopic metal or semiconductor particles involving only a few atoms. The advantage of fabricating such devices is that transistors may be made exceedingly small because the charge storage structures have nanometer size. However, in fabricating such devices many times photolithography is used to form structures around the nanocrystals. This limits the minimum size for memory transistors because the device is subject to the resolution limits of photolithography. Nevertheless, even with such limits, very small devices of great utility may be made.
For example, in U.S. Pat. No. 6,054,349 to Nakajima et al. discloses a single electron device having an insulated film on a substrate with a plurality of nanometer size conductive particles formed in the insulating film in an interface between the substrate and the insulating film. The conductive particles are effective for trapping single electrons for charge storage purposes in a memory transistor. A similar structure is shown in U.S. Pat. No. 6,320,784 to Muralidhar et al. The device features a substrate with source and drain regions, a tunnel dielectric above the substrate and between the source and drain, and a floating gate over the tunnel dielectric. Electrons for charge storage are pulled from the substrate by a control gate.
The beauty of nanocrystal structures of the prior art is that nonvolatile memories can be formed, particularly EEPROM transistors of very small size, low power dissipation, and with simple fabrication techniques.
An object of the invention was to devise an improved transistor device employing nanocrystal charge storage.
The above object has been achieved in a nanocrystal transistor which uses a floating gate as a charge storage region, transferring charge through a tunneling barrier to nanocrystals. Unlike the prior art, where charge has been pulled from the substrate, the present invention relies on a separate charge reservoir, which can be doped specifically for charge supply, while the substrate is doped for conductivity between source and drain electrodes. By pulling charge from the charge reservoir to a separated nanocrystal layer, the electrostatic properties of the nanocrystal layer are modified, influencing a subsurface channel between source and drain in a MOS transistor. So unlike the prior art, where the nanocrystals themselves exert direct influence on the channel, the present invention is just the opposite. The nanocrystals are used to modify electrostatic properties of a separated region and then directly influence channel behavior in the usual way, characteristic of a MOS transistor. In the simplest mode of operation, a threshold may be established for charge transfer from the charge supply layer to the nanocrystal layer and this threshold is similar to the threshold of non-volatile memory transistors. However, further voltage changes will cause further electron transitions from the charge supply layer to the nanocrystal layer whereby the conductivity of the channel is changed in a stepwise manner, like modulation. Reverse voltages will cause depletion of the nanocrystal layer, driving electrons from the nanocrystal layer back to the charge supply layer. This modulation of the channel allows the transistor to behave as an amplifier in another mode of operation wherein channel conductivity tracks the input signal. Conduction between source and drain amplifies the gate voltage in the amplifier mode or senses the pinch-off characteristic in the memory mode. Multiple levels of pinch-off may be sensed so that multilevel storage may be achieved.